In a semiconductor memory such as a dynamic random access memory (DRAM) IC, the time it takes to activate a wordline over its entire length is one of the most significant contributors to the total (off-chip) access time. The wordline activation delay is influenced by several parameters including the length and width of the wordline, the number of devices accessed thereby, and the thickness of the device gate oxide. Longer, narrower wordlines take longer to fully activate because of the greater RC time constant associated therewith.
As devices become ever more densely packed in memory ICs, longer, proportionally narrower wordlines will be required to serve even greater numbers of devices. Consequently, the wordline activation delay will become an even greater contributor to the total off-chip access time.
In an effort to decrease the off-chip access time, various schemes have been used to more accurately estimate the delay in activating a wordline. Simplified for functional purposes, the wordline activation delay is modeled as the amount of time required for 1) row predecoded address signals to propagate through the spine of a dual memory unit; and then 2) be decoded so as to activate the selected wordline driver (at which time the voltage is raised on the wordline); and then 3) for the raised voltage to propagate to the selected column location (at which time complementary signals develop on the selected bitline pair which can be latched by a sense amplifier). Thus, the wordline activation delay is modeled as the total amount of delay between the presentation of row predecoded address signals in the spine to the development of the complementary bitline voltages upon accessing the selected memory cell.
Various schemes have been used or proposed to estimate the wordline activation delay. Hardwired random wordline delay monitors have been utilized to monitor the particular delay in activating each distinct wordline in the memory array.
An example of a prior art sample wordline delay monitor (SWLM) will now be described with reference to FIG. 1. In the prior art example shown in FIG. 1, the sample wordline 202 is located in a separate sample wordline array (SWLA) 200 which is not closely associated with any array 210 in which actual data is stored (arrays 210 are hereinafter referred to as "data-storing arrays"). The data-storing arrays 210 and the row decoder and wordline driver 220 are not part of the circuit which estimates the sample wordline activation delay.
The wordline activation delay is estimated by raising the voltage at a first end 204 of a sample wordline 202, waiting for the raised voltage to propagate the length of the sample wordline, and then triggering a sense amplifier enable (SAE) signal at a fixed delayed interval after the raised voltage reaches a second end 206 of the sample wordline. Since the data-storing arrays 210 and the row decoder and wordline driver circuitry 220 form no part of the sample wordline delay monitor circuit, considerable imprecision results. In order to assure that sense amplifiers are enabled only after the selected wordline is fully activated, the prior art sample wordline delay monitor must accommodate the aggregate of delays from several sources. This aggregate includes the maximum wordline delay which might occur within any data-storing array 210, as calculated when plans for the IC memory are under design, the delay in propagation of signals through the row decoder and wordline driver 220, and an additional interval to allow for variations in the manufacturing process or in operating conditions. To factor in such delays and potential variations in delay, the prior art sample wordline delay monitor includes a delay line 230 which subjects the SAE signal to a large fixed delay.
Due to variability in the manufacturing process and in device parameters which occur over different portions of the IC, the activation delay of a sample wordline in such scheme might not accurately reflect the worst case activation delay, especially when the selected wordline and the sample wordline lie at very different physical locations far from each other. Moreover, the decoding scheme used to activate the sample wordline delay monitor may vary significantly from that used to activate the selected wordline. Therefore, in such existing sample wordline monitoring circuits, the estimated activation delay has been associated with a wide margin of error.
Accordingly, an object of the invention is to provide a sample wordline delay monitor which more accurately reflects an actual delay in activating a wordline within a semiconductor memory.
Another object of the invention is to provide a sample wordline delay monitor which utilizes decoding circuitry which more closely matches that of the particular selected wordline which is activated.
Still another object of the invention is to provide a sample wordline delay monitor which monitors an activation delay on a sample wordline which is located within the same bank of a multiple bank semiconductor memory.
A further object of the invention is to provide a sample wordline delay monitor which monitors an activation delay on a sample wordline which is located within a paused subarray of a memory bank wherein a selected wordline is activated in another subarray of the same bank.
Another object of the invention is to provide a robust sample wordline delay monitor which incorporates a sample wordline redundancy which, in case of malfunction in a sample wordline monitoring path, can be used in place of the sample wordline.
Still another object of the invention is to provide an arrangement of interleaved sample wordlines which are each used on alternate successive memory accesses to the same memory bank to reduce stress and extend the life of individual sample wordlines.